Field of the Technology
This invention relates to a non-volotile memory control circuit which drastically improves reliability of memory retention of a non-volatile memory device.
Background
A non-volatile memory device is now well known as a circuit element which retains memory contents semipermanently. In fact, it is not avoidable that memory states gradually change as time passes. The non-volatile memory devices of semiconductor are largely classified into the following three groups:
(i) ROM . . . read only memory, wherein logic levels are fixed during the masking process and once data are programmed, reprogramming is not possible, PA1 (ii) EPROM . . . erasable programmable ROM, wherein data can be electrically programmed, but data can only be erased by X-ray or ultraviolet light (UV), PA1 (iii) EAROM . . . electrically alterable ROM, wherein information is introduced by selectively programming "1"s in proper bit locations and the bit pattern can be erased later and a new pattern can then be written into the devices.
For the non-volatile memory devices grouped in (i), there are a mask ROM and a fuse ROM. In these memory devices, once the data are programmed, they can not be reprogrammed, and accordingly there arises no problems in practical use even if memory states change as time passes. On the contrary, in the non-volatile memory devices where data information can be reprogrammed, there arise grave problems in practical use when the memory states change as time passes.
This inconvenience is explained referring to FIG. 1, which shows relationship between memory level (M) for example, electric potential or magnetic potential, and time lapse (T). The memory level shown by a curve M1 indicates a memory state 1 (hereinafter written "1"), and the memory level shown by a curve MO indicates a memory state 0 (hereinafter written "0"). The memory levels for "1" and "0" have their initial values M10 and M00 (at T0), respectively, and slowly change as time passes as shown in FIG. 1. They reach M11 and M01 at T1, and reach M12 and M02 at T2, respectively.
Theoretically speaking, it is possible to distinguish between "1" and "0", if the memory level M1 for "1" and the memory level for "0" satisfy the relationship .vertline.M1-M0.vertline.&gt;0. But this is only theoretical relation, and in practice accuracies of an interrogation circuit or the like used must be taken into account. Accordingly, specified difference .DELTA.M is required between the memory level M1 for "1" and the memory level M0 for "0". This means, distinction between "1" and "0" is surely possible when the relation .vertline.M1-M0.vertline..gtoreq..DELTA.M holds for the memory levels M1 and M0, where the difference .DELTA.M is a positive and finite value.
For the characteristics of a non-volatile memory device, the longer the time period from a writing to the time for the memory level difference becoming to the value .DELTA.M is, and also the smaller the minimum value of the memory level difference .DELTA.M required for an accurate reading of "1" and "0" is, the longer the time of memory retention becomes.
In actual memory devices, as far as the memory levels M1 and M0 change as time passes shown in FIG. 1, a maximum memory retention time becomes a finite one. For example, if a difference .DELTA.M(2) at T2 is equal to the threshold value of the difference of the memory levels .DELTA.M which is necessary to distinguish between "1" and "0", then we can define T2 as the memory retention time of the non-volatile memory devices. Accordingly, if the memorized memory levels can be reprogrammed before the quantity .vertline.M1-M0.vertline. decreases to the threshold value .DELTA.M(2), the valid memory states can be continuously retained.